Method
Formal verification
Overview
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of a system with respect to a certain formal specification or property, using formal methods of mathematics.
Formal verification is a key incentive for formal specification of systems, and is at the core of formal methods.
It represents an important dimension of analysis and verification in electronic design automation and is one approach to software verification. The use of formal verification enables the highest Evaluation Assurance Level (EAL7) in the framework of common criteria for computer security certification.
Formal verification can be helpful in proving the correctness of systems such as: cryptographic protocols, combinational circuits, digital circuits with internal memory, and software expressed as source code in a programming language. Prominent examples of verified software systems include the CompCert verified C compiler and the seL4 high-assurance operating system kernel.
The verification of these systems is done by ensuring the existence of a formal proof of a mathematical model of the system. Examples of mathematical objects used to model systems are: finite-state machines, labelled transition systems, Horn clauses, Petri nets, vector addition systems, timed automata, hybrid automata, process algebra, formal semantics of programming languages such as operational semantics, denotational semantics, axiomatic semantics and Hoare logic.
Overview adapted from Wikipedia (CC BY-SA 4.0; see the article history for authors).
Possible passages
Found by search and not yet checked by a person; they may only mention the idea in passing.
227.] Finite Cognition, when it pre-supposes what is distinguished from it to be something already existing and confronting it,--to be the various facts of external nature or of consciousness--has, in the first place, (1) Formal identity or the abstraction of universality for the form of its action. Its activity therefore consists in analysing the given concrete object, isolating its differences, and giving them the…
Georg Wilhelm Friedrich Hegel, The Logic of Hegel
States what Formal verification is.
Simplicity and objectivity do not have to be secured through elaborate and labored metaphysical construction. The data are simple and the hypothesis objective in so far as they accomplish the work where unto they are called--the removal of conflict, ambiguity, and inhibition in conduct and affection. In the experimental conception of inference it is clear that the principles of formal logic must play their role…
John Dewey, Creative Intelligence
States what Formal verification is.
This is nothing else than the necessity of abstract logic, which is the presupposition involved in the very fact of interrelated existence as disclosed in each immediate occasion of experience. The key to the pattern means this fact:—that from a select set of those general conditions, exemplified in any one and the same occasion, a pattern involving an infinite variety of other such conditions, also exemplified in…
Alfred North Whitehead, Science and the modern world
States what Formal verification is.
Related ideas
- Proof assistant
- Mathematics
- Automated theorem proving
- Soundness
- Temporal logic
- Compiler
- Rocq
- Linear temporal logic
- Formal methods
- Isabelle (proof assistant)
- Formal specification
- East China Normal University
- Property Specification Language
Place in the tradition
Part of First-order logic.